| Description |
GaAs is considered as a novel channel material in complementary metal-oxide¬semiconductor (CMOS) technology to replace Si due to its high electron mobility. However, unlike SiO2 on Si, formation of poor quality native oxides, such as As-O and Ga-O between gate dielectric and GaAs is the major obstacle in realizing GaAs based MOS devices. The Fermi level pinning in GaAs MOS devices is associated with these native oxides. The Fermi level pinning at the dielectric and semiconductor interface introduces various instabilities such as drain current drift, high hysteresis, large leakage current, etc., which limit the performance and reduce the life time of metal-oxide-semiconductor field effect transistors (MOSFETs). Thus interface passivation is a prerequisite before dielectric deposition. Surface passivation of GaAs wafers was done by sulfur, and MOCVD grown epitaxial ZnO (1.8 nm) and InP (1.5 nm) layers. GaAs MOS devices were fabricated using ZrO2 high-k dielectric material. The high-k/GaAs interface was studied by x-ray photoelectron spectroscopy (XPS), deep level transient spectroscopy (DLTS), and high-resolution transmission electron microscope (HRTEM). Several electrical characteristics such as capacitance-voltage (C-V), current density-voltage (J-V), and charge trapping characteristics of high-k/GaAs MOS devices were performed to understand the effect of ultrathin passivation on GaAs. As an application, GaAs MOS based nonvolatile memory (NVM) devices were fabricated and characterized. MOCVD grown 5 nm InP quantum dots (QDs) were embedded as charge storage elements between high-k control and tunneling dielectric layers, both being ZrO2. The aim is to achieve lower programming voltage and good retention property to replace conventional Si based devices, and to observe the capability of InP QDs as charge storage elements instead of using metallic nanoparticles, which act as trap states influenced by quantum confinement
|