ASET Colloquium

Design and development of FPGA based PCI Express card

by Mr. Sunil G. Kulkarni (Pelletron, BARC/TIFR)

Friday, January 21, 2011 from to (Asia/Kolkata)
at Colaba Campus ( AG-66 )
Description
The talk discusses development of an 8 lane PCI Express digital I/O interface card, which can be used for variety of applications requiring high speed data transfer to PC. This new serial bus lane-wise architecture with scalability has many advantages over conventional parallel PCI bus. Applications requiring low speed can use only one lane of PCI Express wherein applications requiring high speed can use 2, 4, 8, 16 or 32 lanes of PCI Express depending on the speed requirement. Each serial lane of PCI Express has data transfer speed of 2.5 Giga bits per second and is duplex (can communicate in two directions simultaneously). This next generation bus does not define physical layer due to which data transfer can take place using copper wire or optical cables. 

Material:
Organised by Dr. Satyanarayana Bheesette